Computational Logic Inc. Publications

Electronic versions of some of these papers are available from CLI's World Wide Web server.

1. Russinoff, David M.: Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits. NASA Contractor Report 191608, January 1995.

2. Russinoff, David M.: A Formal Language for the Specification and Verification of Synchronous and Asynchronous Circuits. NASA Contractor Report 191509, September 1993.

3. Moore, J Strother: A Formal Model of Asynchronous Communication and Its Use in Mechanically Verifying a Biphase Mark Protocol. NASA Contractor Report 4433, June 1992.

4. Moore, J Strother: Mechanically Verified Hardware Implementing an 8-bit Parallel IO Byzantine Agreement Processor. NASA Contractor Report 189588, Apr. 1992.

5. Young, William D.: Verifying the Interactive Convergence Clock Synchronization algorithm Using the Boyer-Moore Theorem Prover. NASA Contractor Report 189649, April 1992.

6. Brock, Bishop; and Hunt, Jr., Warren A.: Report on the Formal Specification and Partial Verification of the VIPER Microprocessor. NASA Contractor Report 187540, July 1991.

7. Bevier, William R.; and Young, William D.: The Proof of Correctness of a Fault-Tolerant Circuit Design. In Second IFIP Conference on Dependable Computing For Critical Applications, Tucson, Arizona, Feb. 1991, pp. 107-114.

8. Bevier, William R.; and Young, William D.: Machine Checked Proofs of the Design and Implementation of a Fault-Tolerant Circuit. NASA Contractor Report 182099, Nov. 1990.